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              PACT 2005 WORKSHOPS -- CALL FOR PAPERS/PARTICIPATION

Saturday (September 17)

Morning:

W1: Workshop on Operating System Interference in High Performance  
Applications (OSIHPA)
Organizers: Ronald Mraz, IBM T.J. Watson / Ronald Minnich, LANL /
            Fabrizio Petrini, LANL

http://research.ihost.com/osihpa/index.html

High performance applications require efficient coordination of  
execution between parallel processes to insure that high bandwidth,
low latency communications can be utilized to the fullest potential.
Having the individual components of a parallel application depended
upon uncoordinated efforts of commodity operating system schedulers
can reduce the performance of a parallel machine
significantly. Furthermore, the performance can be reduced to the
point that scalability is impaired. The goal of the workshop is to
better understand the impact that operating system interference has on
multithreading, increased scalability and other new technologies.

In this workshop, we seek to bring together diverse participants who
are managing this problem through hardware, scheduling, operating
systems and compilers. We encourage active participation from
processor architects, system architects, operating systems designers,
virtual machine architects, compiler writers, performance analysts,
and developers.

Afternoon:

W2: Workshop on Memory Performance: Dealing with Applications,  
Systems, and Architecture (MEDEA)
Organizers: Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi,  
            and Antonio Prete, University of Pisa, Italy

http://garga.iet.unipi.it/medea05/

MEDEA-2005 Workshop wants to be a forum for academic and industrial  
people to meet, discuss and exchange their ideas, experience and
solutions in the design and evaluation of architectures for embedded,
commercial and general purpose systems aimed to address memory
performance issues.

Typical architectural choices include single processor
vs. multiprocessor/multicore solutions, traditional vs. clustered
architectures, superscalar, multithreaded or VLIW architectures with
emphasis on single chip design. Application domains encompass
commercial (Web, DB, and multimedia), embedded (personal, mobile,
automotive, automation and medical), networking applications, etc.


Sunday (September 18)

Morning:

W3: Workshop on Binary Instrumentation and Applications (WBIA)
Organizers: Robert Cohn, Intel / David Kaeli, Northeastern University

http://www.ece.neu.edu/conf/WBIA/

This workshop provides a forum for researchers to present their work  
on binary instrumentation systems and applications. Binary
instrumentation has been shown to be an effective technique to support
program analysis, debugging, security, and simulation. A number of
binary instrumentation tools and runtime systems have been
developed. Binary instrumentation can be effectively implemented
statically (at compile or link time) or dynamically (at run
time). This workshop will provide researchers with an opportunity to
exchange ideas and learn about new tools and applications.

Full day:

W4: Workshop on Storage Network Architecture and Parallel I/O (SNAPI)
Organizers: Qing (Ken) Yang, University of Rhode Island / Hong Jiang,  
University of Nebraska-Lincoln

http://rcf.unl.edu/abacus/SNAPI_05/

Data are the "life-blood" of computing and the main asset of any  
organization. Therefore, disk I/O and data storage on which data
reside are becoming "first class citizens" in today's information
world. This workshop intends to bring together researchers and
practitioners from academia and industry to discuss cutting edge
research on parallel and distributed data storage technologies. By
discussing ongoing research, the workshop will expose participants to
the most recent developments in storage network architectures and
parallel I/O.